A Low Power, High Frequency and High Precision  Multiplier Architecture in GF(p)

Abdoul Rjoub and Lo'ai A. Tawalbeh


A high bit modular multiplier architecture is presented in this paper. The design is based on Radix-4 Montgomery multiplication algorithm that uses two types of digit recoding which results in a competitive design. For an efficient design, the power dissipation as well as circuit speed and area should be considered at the architectural level. We showed in previous publications that radix-4 multiplier operates at high speed and has relatively

small area which makes it the best solution in many arithmetic-dependent applications, such as public-key cryptography algorithms and signal processing applications. In this paper, we are investigating the power dissipation of the proposed architecture and we are presenting the hardware components using transmission gates which reduces the power dissipation. Experimental results are shown to compare our design with previously proposed ones in terms of speed and power dissipation.

31 Oct. 2005